As modern integrated circuits shrink in size, the associated features shrink in size as well. As transistors shrink, features such as through vias and other interconnect elements shrink in size as well. In many instances, various layers of circuit on chips, dies, in packages, on PCBs and other substrates are interconnected between various layers by way of vias. Vias can be formed in openings through a substrate filled with a conductive metal. Typically, the vias are connected to traces or other conductive structures to permit non-aligned contact points in different layers to be connected.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.